发明名称 SEMICONDUCTOR CHIP, STACKED MODULE, AND ELECTRONIC APPARATUS
摘要 PROBLEM TO BE SOLVED: To suppress waste of a chip area by suppressing an increase of the chip area that a through hole occupies. SOLUTION: An apparatus is provided with a silicon substrate 1 where the through hole 9 which vertically passes through is formed, a conductor 2 with which an inner part of the through hole 9 is filled and is exposed to a lower face of the silicon substrate 1 so that it is electrically connected to a device arranged on a lower side of the semiconductor chip 10, an insulating film 3 formed on the silicon substrate 1 so that it covers an upper part of the through hole 9, and an electrode pad 4a arranged on the insulating film so that it is electrically connected to a device arranged on an upper side of the semiconductor chip 10. The through hole 9 and the electrode pad 4a are arranged in mutually overlapped positions in a vertical direction. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004207264(A) 申请公布日期 2004.07.22
申请号 JP20020370923 申请日期 2002.12.20
申请人 NOKIA CORP 发明人 HANAWA TAKESHI
分类号 H01L23/52;H01L21/3205;H01L25/065;H01L25/07;H01L25/18;(IPC1-7):H01L25/065;H01L21/320 主分类号 H01L23/52
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