| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce jitter affecting an S/N ratio. <P>SOLUTION: For example, a PLL circuit for generating a clock signal suitable for a system including CODEC for a sound signal and an audio signal is provided with: a phase comparator which has a hysteresis characteristic and a dead zone and generates a frequency division ratio control signal corresponding to the phase difference between a transfer clock and an I/F clock; a variable frequency divider which frequency-divides a master clock by a frequency dividing ratio which is set in accordance with the frequency division ratio control signal supplied from the phase comparator and generates a sampling clock; and a clock generator which frequency-divides the sampling clock supplied from the variable frequency divider by the prescribed frequency dividing ratio and generates the I/F clock. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
