| 摘要 |
<P>PROBLEM TO BE SOLVED: To further reduce EMI by eliminating the limitation for a phase range for a clock signal, to be selected in a modulation clock signal generating circuit. <P>SOLUTION: The device is first clock selection signals SEL 1-SEL 6 for instructing to select any of the clock signals among m phase clock signal generating means 101 and m phase clock signals CK1-CK6 and constituted with a control means 104 for sequentially outputting first clock selection signals, corresponding to each of the m phase clock signals; an edge emergence timing adjustment arranging means 103 for outputting second clock selection signals SSEL1-SSEL6, corresponding to each of the m phase signals outputted from an m phase clock generator 101; and a modulation clock signal generating means 102 for selecting the clock signal out of the m phase clock signals, based on an activation state in the second clock selection signals SSEL1-SSEL6 outputted from the edge emergence timing adjusting means 103 and outputting a frequency clock signal MCK. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
