| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of necessary wiring layers without increasing the chip area in a magnetic memory device. SOLUTION: In each memory cell line, the source areas of the access transistors are electrically connected to each other by N<SP>+</SP>diffusion node NSL0<x>, NSL1<x> disposed being extended in a line direction. The N+diffusion mode NSL is connected to a main word line/MWL<x> set to an L level (ground voltage Vss) when a corresponding memory cell line is selected. In response to the setting of the main word line/MWL<x> to the L level, the word lines WL0<x>, WL1<x> of an x line are set to H levels in reading data, and the digit lines DL0<x>, DL1<x> of the x line are set to H levels in writing data. COPYRIGHT: (C)2004,JPO&NCIPI
|
