| 摘要 |
Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing cells (71-76) has a pre-defined division ratio and comprises a clock input (CKi) for receiving an input clock (CKin); a divided clock output (CKi+1) for providing an output clock (CKout) to a subsequent frequency dividing cell; a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus further comprises a latch (77) for altering the division ratio and-a D-Flip-Flop (50) circuitry with two latches (51, 52). The first latch (51) is clocked by a first signal (CK3) and the second latch (52) is clocked by a second signal (CK1), whereby the frequency of the first signal (CK3) is lower than the frequency of the second signal (CK1).
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