SigmaDelta MODULATOR OF PLL CIRCUIT

摘要

A SigmaDelta modulator for producing a modulation signal that modulates the frequency division ratio of a comparison frequency divider of a PLL circuit. A plurality of integrators (9a-9c) connected in series integrate input signals (F), and output overflow signals (OF1-OF3) when the integrated values exceed a predetermined value. Differentiators (10a-10f) forward the overflow signals (OF1-OF3) of the integrators (9a-9c). An adder (51) multiplies output signals (a-f) of the differentiators by predetermined factors and adds the multiplied values together. The absolute values of the predetermined factors of the adder (51) are set to be less than a predetermined value. This setting reduces the modulation width of the modulation signal.