发明名称 |
Low power logic gate |
摘要 |
The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines. The plurality of address lines are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.
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申请公布号 |
US2004141400(A1) |
申请公布日期 |
2004.07.22 |
申请号 |
US20030347723 |
申请日期 |
2003.01.21 |
申请人 |
KU JOSEPH;EATON JAMES ROBERT |
发明人 |
KU JOSEPH;EATON JAMES ROBERT |
分类号 |
H03K19/20;H03K19/096;H03K19/12;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
H03K19/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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