METHOD FOR FORMING PLUG OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for forming a plug of a semiconductor device is provided to reduce junction leakage current by minimizing the diffusion of As to a source/drain junction region. CONSTITUTION: Gate lines are formed on a substrate(100) by sequentially forming and patterning a gate oxide layer(220), a polysilicon layer(240) and a hard mask(260). A source/drain region is formed in the substrate between the gate lines. A nitride pattern(300a) is formed on the gate line and the source/drain region. An interlayer dielectric(320) is formed on the resultant structure. A contact hole is formed to expose the source/drain region by etching the interlayer dielectric and the nitride pattern. A plug(340) is formed by depositing an amorphous silicon layer using AsH3 as a reaction gas and planarizing.