发明名称 |
Synchronous global controller for enhanced pipeline |
摘要 |
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller. <IMAGE> |
申请公布号 |
EP1376596(A3) |
申请公布日期 |
2004.07.21 |
申请号 |
EP20030014063 |
申请日期 |
2003.06.23 |
申请人 |
BROADCOM CORPORATION |
发明人 |
ANVAR, ALI;WINOGRAD, GIL I.;TERZIOGLU, ESIN |
分类号 |
G06F13/40;G11C5/06;G11C7/10;G11C7/18;G11C7/22;G11C8/00;G11C8/10;G11C11/413;G11C11/419;G11C29/00 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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