发明名称 Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment
摘要 The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit (11),for identifying a signal obtained by demodulating a multilevel orthogonal modulated signal; a clock regenerating circuit (12) for regenerating a signal identification clock for the identifying circuit (11) to supply the clock to the identifying circuit (11); an equalizing circuit (13) for subjecting the demodulated signal to an equalizing process (13). A clock phase detecting unit (14A) detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit (13) and then supplies the phase component to the clock regenerating circuit (11). The phase component of a signal identification clock can be certainly detected and accurately adjusted so that the signal identification clock can be regenerated with high accuracy. <IMAGE>
申请公布号 EP1439659(A1) 申请公布日期 2004.07.21
申请号 EP20040006365 申请日期 1995.11.21
申请人 FUJITSU LIMITED 发明人 IWAMATSU, TAKANORI;KIYANAGI, HIROYUKI
分类号 H04L7/00;H04L7/02;H04L7/027;H04L7/033;H04L27/22;H04L27/38;(IPC1-7):H04L7/02 主分类号 H04L7/00
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