发明名称 Circuit for looping serial bit streams from parallel memory
摘要 A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.
申请公布号 US6766411(B2) 申请公布日期 2004.07.20
申请号 US20020170122 申请日期 2002.06.12
申请人 TERADYNE INC 发明人 GOLDSHLAG NATHAN L
分类号 G06F12/00;G11C7/10;H03M9/00;(IPC1-7):G06F12/00 主分类号 G06F12/00
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