发明名称 Refresh control circuitry for refreshing storage data
摘要 A refresh array activating signal is activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the specific address bit(s) is (are) utilized as upper bit(s) of the refresh address. Thus, in the self-refresh mode, refresh can be performed for a prescribed address region at uniform intervals, with a lengthened refresh interval, consuming less current. A semiconductor memory device is provided which allows current consumption to be distributed on a time basis and to be reduce in a self-refresh mode is provided.
申请公布号 US6765838(B2) 申请公布日期 2004.07.20
申请号 US20020209901 申请日期 2002.08.02
申请人 RENESAS TECH CORP 发明人 MATSUMOTO JUNKO;YAMAUCHI TADAAKI;OKAMOTO TAKEO
分类号 G11C11/407;G11C11/403;G11C11/406;(IPC1-7):G11C7/00 主分类号 G11C11/407
代理机构 代理人
主权项
地址