发明名称 |
Integrated systems using vertically-stacked three-dimensional memory cells |
摘要 |
Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
|
申请公布号 |
US6765813(B2) |
申请公布日期 |
2004.07.20 |
申请号 |
US20020185588 |
申请日期 |
2002.06.27 |
申请人 |
MATRIX SEMICONDUCTOR, INC. |
发明人 |
SCHEUERLEIN ROY E.;TRINGALI J. JAMES;LYSAGHT COLM P.;ILKBAHAR ALPER;MOORE CHRISTOPHER S.;FRIEDMAN DAVID R. |
分类号 |
G11C5/02;G11C5/06;(IPC1-7):G11C5/02 |
主分类号 |
G11C5/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|