发明名称 Substrate pads with reduced impedance mismatch and methods to fabricate substrate pads
摘要 To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.
申请公布号 US6765298(B2) 申请公布日期 2004.07.20
申请号 US20010013326 申请日期 2001.12.08
申请人 NAT SEMICONDUCTOR CORP 发明人 CHIN TSUN-KIT;LANDUCCI WILLIAM
分类号 H01L23/538;H01L23/64;H05K1/00;H05K1/02;H05K1/11;H05K1/16;(IPC1-7):H01L23/48;H01L27/10;H01L23/12 主分类号 H01L23/538
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