发明名称 Semiconductor memory device with efficient buffer control for data buses
摘要 A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.
申请公布号 US6765843(B2) 申请公布日期 2004.07.20
申请号 US20030369562 申请日期 2003.02.21
申请人 FUJITSU LIMITED 发明人 MORI KAORU;MABUCHI SHUJI
分类号 G11C11/417;G11C7/10;G11C8/12;G11C11/41;(IPC1-7):G11C8/00 主分类号 G11C11/417
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