SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINE BOOSTING SCHEME CAPABLE OF MAXIMIZING BOOSTING LEVEL OF BIT LINE AT LOW VOLTAGE CONDITION

摘要

PURPOSE: A semiconductor memory device having a bit line boosting scheme is provided to maximize a boosting level of a bit line at a low voltage condition. CONSTITUTION: A memory cell array(21) includes a number of memory cells(MC0-MCn). A bit line(BL) is connected to the memory cell array. Boosting capacitors(22,23) are connected to the bit line and boost a voltage of the bit line in response to a boosting driving signal. A bit line sense amplifier(24) senses and amplifies a voltage difference between the bit line and its complementary bit line(BLB). And the boosting capacitor is formed with a depletion NMOS transistor having a negative threshold voltage.