| 摘要 |
<P>PROBLEM TO BE SOLVED: To ensure high reliability and noise canceling power while digitally rejecting noise superposed on a digital signal. <P>SOLUTION: D type flip-flops (DFF) 14 and 16 output signals S14 and S16 produced by delaying an input signal Sin every specified periods. If the signals S14 and S16 have an identical level, a combination circuit 2 sets a signal S2 at that identical level otherwise sets the signal S2 at the level of an output signal Sout in current period. That signal S2 is latched in a DFF 32 upon start of next period and delivered as the output signal Sout. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
