发明名称 |
Variable duty cycle clock generation circuits and methods and systems using the same |
摘要 |
A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.
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申请公布号 |
US2004135608(A1) |
申请公布日期 |
2004.07.15 |
申请号 |
US20020200824 |
申请日期 |
2002.07.22 |
申请人 |
CIRRUS LOGIC INC |
发明人 |
PILLAY SANJAY;MAI KHOI;ZHENG LUO;PANTELAKIS DIMITRI |
分类号 |
G11B;H03K3/017;H03K5/04;H03K5/156;(IPC1-7):H03K3/017 |
主分类号 |
G11B |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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