发明名称 |
MEMORY ARCHITECTURE WITH SERIES GROUPED MEMORY CELLS |
摘要 |
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area. |
申请公布号 |
WO2004059739(A2) |
申请公布日期 |
2004.07.15 |
申请号 |
WO2003EP14637 |
申请日期 |
2003.12.19 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
HILLIGER, ANDREAS;BRUCHHAUS, RAINER;WOHLFAHRT, JOERG |
分类号 |
G11C11/22;H01L21/8242;H01L21/8246;H01L27/108;H01L27/115;(IPC1-7):H01L27/115 |
主分类号 |
G11C11/22 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|