发明名称 METHOD HAVING DYNAMICALLY SCALABLE CLOCK DOMAIN TO SELECTIVELY INTERCONNECT SUBSYSTEMS THROUGH SYNCHRONOUS BUS, AND SYSTEM THEREOF
摘要 <p><P>PROBLEM TO BE SOLVED: To solve problems which are necessary to improve flexibility of operating frequencies of a synchronous bus. <P>SOLUTION: In one mode of this invention, the method for communicating between subsystems coupled to a bus of a computer system on an integrated circuit chip includes a step which makes the subsystems operate by independent clock frequencies when the subsystems do not communicate each other through the bus. A selected pair of the subsystems is made to operate by a shared clock frequency by selectively varying the frequency of a clock signal supplied to the subsystems, and the selected subsystems are enabled to communicate each other by the shared clock frequency through the bus (The clock frequency is different when the pair of subsystems is different.); and the subsystem are made to enable to operate by an independent clock frequency when the subsystem does not communicate to other subsystem. Communication between subsystems is performed by bus-based protocol; as the result, when a subsystem is permitted to access to the bus, the subsystem can use the bus exclusively. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p>
申请公布号 JP2004199664(A) 申请公布日期 2004.07.15
申请号 JP20030394561 申请日期 2003.11.25
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CARPENTER GARY D;CHANDRA VIKAS
分类号 G06F1/06;G06F1/08;G06F1/10;G06F1/12;G06F1/24;G06F13/364;H04L12/28;(IPC1-7):G06F1/08 主分类号 G06F1/06
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