| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock control circuit and an interface circuit capable of reducing power consumption more than that realized by a normal standby function. <P>SOLUTION: In the clock control circuit and the interface circuit, a clock enabler 203 which generates a second clock CLK by being synchronized with a first clock CLKA and supplies it to a processing circuit when an active clock enable signal is received, an edge detection part 201 which detects changeover timing to a start bit included in inputted data by being synchronized with the first clock, a clock control part 202 which activates a clock enable signal, outputs it to the clock enabler 203 when a detection signal is received and inactivates the clock enable signal when an active noise signal is received and a noise discrimination part 204 which is operated by receiving the second clock CLK, activates the noise signal and outputs it to the clock control part 202 when noise is detected after elapse of prescribed time from starting timing of the detection signal are provided. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
