| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache coincident control capable of preventing lowering of cache access throughput and increasing of network loads in a computer system for activating a plurality of OSs on a single multi-processor system. SOLUTION: In the multi-processor system in which a processor, nodes and a shared memory are connected with one another via a mutual coupling network, a plurality of logical partitions (LPAR) can be set by system management software, a part of resources of a multi-processor is allocated to the respective LPARs, the OSs can independently be activated by the respective LPARs, the respective nodes are provided with cache coincident control circuits and registers which store information by which the nodes in which the resources in the LPARs exist can be identified by every processor or every IO device in the nodes, in accessing the shared memory, the cache coincident control circuit performs the cache coincident control to the nodes in which the processor or the IO device sharing a memory area with the processor exist by referring to the registers. COPYRIGHT: (C)2004,JPO&NCIPI
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