发明名称 |
Method and apparatus for efficient bi-linear interpolation and motion compensation |
摘要 |
A method and apparatus for performing bi-linear interpolation and motion compensation including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two or more lines of 2n+1 content byte elements may be shuffled to generate a first and second packed data respectively including at least a first and a second 4n byte elements including 2n-1 duplicated elements. A third packed data including sums of products is generated from the first packed data and packed byte coefficients by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements and packed byte coefficients by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed, and may be rounded and averaged.
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申请公布号 |
US2004139138(A1) |
申请公布日期 |
2004.07.15 |
申请号 |
US20030687953 |
申请日期 |
2003.10.17 |
申请人 |
CHEN YEN-KUANG;YEUNG MINERVA M. |
发明人 |
CHEN YEN-KUANG;YEUNG MINERVA M. |
分类号 |
G06F9/30;G06F9/302;G06F9/308;G06F9/315;G06F9/38;G06F17/14;(IPC1-7):G06F7/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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