发明名称 |
Optimizing designing apparatus of integrated circuit, optimizing designing method of integrated circuit, and storing medium in which program for carrying out optimizing designing method of integrated circuit is stored |
摘要 |
It is an object of the present invention to provide a method, an apparatus and a program having high optimization precision and capable of obtaining an answer required by a designer in a short time by combining optimization between individual transistors and optimization as the entire circuit, or by appropriately combining judgment of an operation region, an analysis of the operation region and a SWEEP sensitivity analysis when the optimization is carried out. An optimizing designing apparatus of an integrated circuit for designing a circuit, comprises operation region judging means for adjusting an operation region (linear region, saturation region) of the circuit, operation region analysis means for displaying liner characteristics (Ids-Vgs characteristics) of the circuit and saturation characteristics (Ids-Vds characteristics) of the circuit, and SWEEP sensitivity analysis means for displaying variation in output characteristics of the circuit.
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申请公布号 |
US2004139405(A1) |
申请公布日期 |
2004.07.15 |
申请号 |
US20030745648 |
申请日期 |
2003.12.29 |
申请人 |
SIPEC CORPORATION;SEIKO INSTRUMENTS INC. |
发明人 |
MORI KENJI;NAKAJIMA TAKASHI |
分类号 |
G06F17/50;H01L21/82;H03K19/00;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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