发明名称 Semiconductor memory
摘要 A fault after an assembling process is saved by using a tester. An error detector circuit compares read data from a memory cell and data from an external input/output terminal by means of a comparator circuit, thereby determining whether a memory cell is good or faulty. The error detector circuit outputs a sense signal COMPERR in the case where the memory cell is faulty. A self fuse program circuit causes a latch circuit LAi to latch an external address as a save address upon receipt of the sense signal COMPERR. By a counter Ci and a switch circuit SW, programming of a save address is carried out by transferring the save address latched at the latch circuit LAi to a fuse program circuit FPi on one bit by one bit basis.
申请公布号 US2004136248(A1) 申请公布日期 2004.07.15
申请号 US20030724565 申请日期 2003.11.26
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KOZUKA EIJI
分类号 G11C29/04;G11C7/10;G11C29/00;G11C29/12;(IPC1-7):G11C7/00 主分类号 G11C29/04
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