发明名称 Synchronising circuit
摘要 In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronised with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronised with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.
申请公布号 US2004135602(A1) 申请公布日期 2004.07.15
申请号 US20030624280 申请日期 2003.07.22
申请人 WARD RICHARD;SURACE GIUSEPPE;JOY ANDREW 发明人 WARD RICHARD;SURACE GIUSEPPE;JOY ANDREW
分类号 H04L7/00;H04L25/14;(IPC1-7):H03L7/00 主分类号 H04L7/00
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