| 摘要 |
PROBLEM TO BE SOLVED: To solve a problem wherein it is difficult to minimize a dispersion in film thickness because the polishing rate of a CVD oxide film is changed by a field pattern at the time of forming STI, and the optimum film thickness of a CVD oxide film and CMP polishing quantity are different in each pattern. SOLUTION: Resist pattern information for the formation of a field pattern in a semiconductor STI forming process and depth data for silicon etching in a post process are inputted to a control part for calculating a pattern effect, the optimum film thickness of an element isolating oxide film and optimum CMP polishing quantity are calculated and the growth of the element isolating oxide film and CMP polishing are performed in an optimum condition to minimize the dispersion in the CVD oxide film thickness of an element isolating part. COPYRIGHT: (C)2004,JPO&NCIPI
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