发明名称 Step-down circuit, power supply circuit, and semiconductor integrated circuit
摘要 A step-down circuit is provided that comprises a clock control circuit which provides a plurality of clock signals having a frequency determined based on a control signal; a charge pump circuit which reduces a first potential applied to a first terminal and then provides a second potential from a second terminal by switching the connection of a plurality of capacitors in sync with a plurality of the clock signals output from the clock control circuit; and a comparator which produces the control signal to be supplied to the clock control circuit by comparing the second potential to a reference potential.
申请公布号 US2004136213(A1) 申请公布日期 2004.07.15
申请号 US20030719998 申请日期 2003.11.21
申请人 FUJISE TAKASHI 发明人 FUJISE TAKASHI
分类号 H02M3/07;H03K19/00;(IPC1-7):H02M3/06 主分类号 H02M3/07
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