| 摘要 |
A circuit for serializing parallel data of N bits, comprises: a first register for storing M bits of the parallel data, M being less than N, the first register being clocked by a first clock; a second register for storing P bits of the parallel data, the second register being clocked by a second clock which is different from the first clock; a third register for storing Q bits of the parallel data, wherein M+P+ Q = N, the third register being clocked by a third clock; and a fourth register for storing data output from the third register. The fourth register is clocked by a fourth clock which is different from the first, second, and third clocks. Logic gates are provided for receiving as inputs the N bits of parallel data output from the first, second, and fourth registers to form N serial data. <IMAGE>
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