发明名称 |
Semiconductor device allowing easy confirmation of operation of built in clock generation circuit |
摘要 |
A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.
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申请公布号 |
US6763079(B1) |
申请公布日期 |
2004.07.13 |
申请号 |
US19990252910 |
申请日期 |
1999.02.19 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
IWAMOTO HISASHI |
分类号 |
G01R31/28;G01R31/317;G11C11/401;G11C11/407;G11C29/02;G11C29/12;H03K5/00;H03K5/13;H03L7/081;H03L7/089;(IPC1-7):H04L7/08 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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