| 摘要 |
A non-power-of-two modulo N Gray-code counter (the "Gray-code counter") and a binary incrementer-decrementer algorithm are disclosed. One embodiment of the Gray-code counter of this invention comprises a Gray-to-binary converter for receiving an M-bit Gray-code input value and converting the M-bit Gray-code input value to an M-bit binary-code input value, IB[m-1:0]; a binary incrementer-decrementer for converting the M-bit binary-code input value to an M-bit binary-code output value, OB[m-1:0], wherein the M-bit binary-code output value will differ from the M-bit binary-code input value by modulo +/-1 for all but one value of the M-bit binary-code input value; a binary-to-Gray converter for converting the M-bit binary-code output value to an M-bit Gray-code output value; and a clocked storage device operably coupled to the binary-to-Gray converter for storing the M-bit Gray-code output value and for providing the M-bit Gray-code output value to the Gray-to-binary converter as a next M-bit Gray-code input value. The binary incrementer-decrementer further comprises an incrementer-decrementer algorithm for skipping certain binary values in order to maintain the Gray-code nature of the counter when translated to Gray-code, while allowing the Gray-code counter to be implemented as a modulo counter of any even size.
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