发明名称 |
Synchronous signal processing system |
摘要 |
A signal processing system includes a PLL circuit for generating a first clock signal based on a system clock signal, a CPU for generating a second clock signal based on the first clock signal and operating with the second clock signal. The PLL circuit receives the second clock signal as a feed-back signal to deliver the first clock signal so that the phases of the second clock signal and the system clock signal coincide with each other. A data path circuit operates with the system clock signal and UDL circuit operates with the second clock signal, whereby the system can be handled as a synchronous circuit operating with the single system clock signal.
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申请公布号 |
US6763080(B1) |
申请公布日期 |
2004.07.13 |
申请号 |
US20000565490 |
申请日期 |
2000.05.05 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
HIGASHINO KIMINORI |
分类号 |
G06F1/10;G06F1/12;H03L7/06;H04L7/033;H04N5/06;H04N5/14;(IPC1-7):H03D3/24 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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