发明名称 Receiving apparatus and array combining method
摘要 A switch 404 sends an output of a reception processing section 402 to a training processing section 405 at a training processing time and to a demodulation processing section 407 by control of a timing control section 403. The training processing section 405 passes received signals through FFFs for the respective branches to perform array combination at the training processing time. A tap coefficient converting section 406 converts the tap coefficient of FFF estimated by the training processing section 405 to calculate a weighting factor. The demodulation processing section 407 weights the received signals using the calculated weighting factor to combine, and passes the combined signal through FFF. This makes it possible to reduce the amount of operations at the array combining time.
申请公布号 US6763077(B1) 申请公布日期 2004.07.13
申请号 US20000586957 申请日期 2000.06.05
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 SAITO YOSHIKO;UESUGI MITSURU
分类号 H01Q3/26;H03H21/00;H04B1/10;H04B7/005;H04B7/08;H04L25/03;(IPC1-7):H04B1/10 主分类号 H01Q3/26
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