发明名称 REGULATOR CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To reduce the power consumption in the form of suppressing an increase in layout area or chip area by enabling the reduction in the layout area or chip area by reducing a necessary resistance, compared with the case using a plurality of independent regulator circuits. <P>SOLUTION: In a first output circuit 1 and a second output circuit 2, standard voltage sources 12 and 22 are connected to the noninverting input ends of arithmetic amplifiers 11 and 21, connecting points of two resistance element constituting resistance dividing circuits 13 and 23 are connected to inverting input ends of the arithmetic amplifiers 11 and 21, and the connecting points of the drain electrodes of transistors 14 and 24 driven by the output of the arithmetic amplifiers 11 and 21 with one-side ends of the resistance dividing circuits 13 and 23 are taken as output ends 15 and 25. The other end of the resistance dividing circuit 13 is grounded. The other end of the resistance dividing circuit 23 is connected to the output terminal 15. <P>COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004192123(A) 申请公布日期 2004.07.08
申请号 JP20020356730 申请日期 2002.12.09
申请人 RENESAS TECHNOLOGY CORP 发明人 TSUCHIYAMA TOMONORI
分类号 G05F1/56 主分类号 G05F1/56
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