发明名称 Computing architecture and related system and method
摘要 A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
申请公布号 US2004133763(A1) 申请公布日期 2004.07.08
申请号 US20030684102 申请日期 2003.10.09
申请人 LOCKHEED MARTIN CORPORATION 发明人 MATHUR CHANDAN;HELLENBACH SCOTT;RAPP JOHN W.;JACKSON LARRY;JONES MARK;CHERASARO TROY
分类号 G06F3/00;G06F3/02;G06F5/00;G06F13/00;G06F15/00;G09G5/00;G11C5/00;G11C7/00;G11C11/22;(IPC1-7):G06F15/00 主分类号 G06F3/00
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