发明名称 |
Semiconductor memory device having a DRAM cell structure and handled as a SRAM |
摘要 |
A semiconductor memory device includes a memory cell array including a plurality of memory cells having a DRAM cell structure and is treated as a SRAM memory device without controlling the data refreshing cycle for the memory cells. The refreshing cycle is separated into a read operation and a write operation, which sandwich therebetween a read/write operation for the input address of the memory cell. The data read in the refreshing cycle is saved in a refreshing sense amplifier during the read/write operation and stored in the memory cell after the read/write operation.
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申请公布号 |
US2004130959(A1) |
申请公布日期 |
2004.07.08 |
申请号 |
US20030739374 |
申请日期 |
2003.12.18 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
KAWAGUCHI YASUNARI |
分类号 |
G11C11/403;G11C11/406;G11C11/409;H01L27/11;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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