| 摘要 |
PROBLEM TO BE SOLVED: To provide a numerically controlled oscillator in which a circuit scale and power consumption are reduced while keeping a requested frequency deviation and the occurrence of spuriousness is suppressed as much as possible. SOLUTION: When defining the sampling frequency of signals as Fs, the upper limit value of the frequency setting interval of the signals as FD and optional integers as K and L, in a phase accumulator 1, a phase computing device 1b adds or subtracts inputted phase difference data and phase data outputted by a phase register 1a by a modulo operation in which a modulus is M to be an integer among M calculated by M=Fs/FD×K/L in, and the a phase accumulator 1 accumulates the phase difference data and generates the phase data. In the meantime, the output terminal of the phase accumulator 1 and the address terminal of a ROM 2 are connected, and amplitude data of the signals set by the frequency setting interval of a dF step calculated by dF=FD/K×L corresponding to the phase data inputted to the address terminal are outputted from the data terminal of the ROM 2. COPYRIGHT: (C)2004,JPO&NCIPI
|
