| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout design method for reducing the load of the layout operation of a power transistor. SOLUTION: This layout design method comprises a process S200 for acquiring gate length L and full gate width W<SB>t</SB>of a power transistor, a process S202 for acquiring the gate width W of a transistor element and a process S204 for acquiring the number of columns N<SB>c</SB>and the number of lines N<SB>r</SB>of the transistor element, and for arranging the transistor element having the gate length L and the gate width W with the number of columns N<SB>c</SB>and the number of lines N<SB>r</SB>to execute the layout of the power transistor when the product of the gate width W, the number of columns N<SB>c</SB>and the number of lines N<SB>r</SB>is not less than full gate width W<SB>t</SB>. COPYRIGHT: (C)2004,JPO&NCIPI
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