发明名称 Sampling/holding method and circuit
摘要 The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1~k. Each sampling unit has input terminals 1-1~k and output terminals 3-1~k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1~k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.
申请公布号 US2004130356(A1) 申请公布日期 2004.07.08
申请号 US20030701647 申请日期 2003.11.05
申请人 HIGASHI KOICHI;MATSUSAKO KYOJI 发明人 HIGASHI KOICHI;MATSUSAKO KYOJI
分类号 G11C27/02;H03K5/00;H03K5/24;H03K17/00;H03M1/00;H03M1/12;(IPC1-7):H03K5/00 主分类号 G11C27/02
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