发明名称 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby
摘要 An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.
申请公布号 US2004129981(A1) 申请公布日期 2004.07.08
申请号 US20030741751 申请日期 2003.12.19
申请人 KIM YOUNG-PIL;JIN BEOM-JUN;KIM HYOUNG-JOON;NAM BYEONG-YUN 发明人 KIM YOUNG-PIL;JIN BEOM-JUN;KIM HYOUNG-JOON;NAM BYEONG-YUN
分类号 H01L21/28;H01L21/20;H01L21/285;H01L21/60;H01L21/768;H01L21/8234;(IPC1-7):H01L29/76 主分类号 H01L21/28
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