| 摘要 |
PROBLEM TO BE SOLVED: To improve CPU performance by effectively utilizing a delay slot of a pipeline stage without containing a branch prediction circuit. SOLUTION: This microprocessor comprises two types of queue buffers 11 and 12, one of which stores a pre-fetched non-branch instruction and the other of which stores a pre-fetched branch target instruction; and a pipeline processing stage (data pass part) having a plurality of processing stages for executing pipeline processing, the processing stages other than the final processing stage being formed in two types. The non-branch instruction and branch target instruction are inputted to the pipeline processing stages formed in two types, respectively, to determine whether the condition of a branch instruction is established or not. On the basis of the determination signal, either one of the two types of processing stages is inputted to the final processing state. COPYRIGHT: (C)2004,JPO&NCIPI
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