发明名称 |
Single event upset hardened latch |
摘要 |
A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.
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申请公布号 |
US2004130351(A1) |
申请公布日期 |
2004.07.08 |
申请号 |
US20030742436 |
申请日期 |
2003.12.19 |
申请人 |
INTEL CORPORATION |
发明人 |
HAZUCHA PETER;SOUMYANATH KRISHNAMURTHY |
分类号 |
H03K3/012;H03K3/037;H03K3/356;(IPC1-7):G01R29/02 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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