发明名称 MECHANISM FOR GATING A RECEIVER TERMINATED CLOCK
摘要 According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock receiver, and clock generator coupled to the one or more clock traces. The clock generator gated clock signals to the first clock receiver in response to detecting that the clock traces have been disconected from electrical ground.
申请公布号 WO03098381(A3) 申请公布日期 2004.07.08
申请号 WO2003US12347 申请日期 2003.04.18
申请人 INTEL CORPORATION 发明人 HORIGAN, JOHN
分类号 G06F1/10;G06F1/32 主分类号 G06F1/10
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