发明名称 Apparatus for selecting test patterns for logic circuit, computer implemented method for selecting test patterns, and computer program product for controlling a computer system so as to select test patterns
摘要 An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configure to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults given the added weight, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.
申请公布号 US2004133833(A1) 申请公布日期 2004.07.08
申请号 US20030678975 申请日期 2003.10.02
申请人 NOZUYAMA YASUYUKI 发明人 NOZUYAMA YASUYUKI
分类号 G01R31/28;G01R31/3183;G06F11/22;G06F11/26;(IPC1-7):G06F11/00 主分类号 G01R31/28
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