发明名称 Compression circuit for testing a momory device
摘要 An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal. A method for testing a memory device having a plurality of data lines includes reading data present on at least a subset of the plurality of data lines. The data associated with at least one data line of the subset is masked. It is determined if the data matches a predetermined pattern. At least a pass signal is provided if the data matches the predetermined pattern.
申请公布号 US2004133828(A1) 申请公布日期 2004.07.08
申请号 US20030712150 申请日期 2003.11.13
申请人 MICRON TECHNOLOGY, INC. 发明人 MERRITT TODD A.;VANHEEL NICHOLAS
分类号 G11C29/40;(IPC1-7):G11C29/00 主分类号 G11C29/40
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