发明名称 CHIP-SIZE PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <P>PROBLEM TO BE SOLVED: To provide a manufacturing method, with which a highly reliable wafer level CSP can be manufactured at low cost, even when using a wafer of large aperture. <P>SOLUTION: A sharpened bump is formed on an electrode pad of a plurality of semiconductor devices integrated into a semiconductor wafer, and a sheet-like sealing resin is stuck on the surface of the wafer to cover the bump. In such a case, the bump is passed through the sheet-like sealing resin, and a tip of the bump is exposed. Thereafter, a wiring metal layer is formed on the surface of the sheet-like sealing resin to be connected with the bump, an external connecting terminal is provided at a predetermined position on the wiring metal layer, and the semiconductor devices are then segmented. <P>COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004193497(A) 申请公布日期 2004.07.08
申请号 JP20020362646 申请日期 2002.12.13
申请人 NEC ELECTRONICS CORP 发明人 ONO YOSHIHIRO
分类号 H01L23/12;H01L21/44;H01L23/31;H01L23/485 主分类号 H01L23/12
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