| 摘要 |
A method of fabricating a gate structure for a MOSFET device, allowing a reduced polysilicon depletion effect as well as increased carrier mobility to be realized, has been developed. The method features a polysilicon-germanium component of the gate structure, sandwiched between an underlying polysilicon seed layer and an overlying polysilicon cap layer. The inclusion of germanium in the deposited polysilicon-germanium component results in enhanced dopant activation and thus a reduced polysilicon depletion effect. The polysilicon seed and cap layers are subjected to low temperature, anneal procedures, performed in situ in a hydrogen ambient, after deposition of the polysilicon layers. The in situ anneal procedures alters the columnar grains of the polysilicon layers to small, random grains, resulting in smooth polysilicon surfaces, with the smooth surface of the polysilicon seed layer interfacing the underlying gate insulator layer resulting in enhanced carrier mobility when compared to counterpart polysilicon seed layer comprised with rough surfaces.
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