| 摘要 |
PURPOSE: A gate driver using an SCLD(Shared Column-Line Driving) method and a driving method thereof are provided to simplify a total structure and stabilize a driving operation by reducing the number of shift registers within the gate driver. CONSTITUTION: A gate driver using an SCLD method includes a shift register, an output controller, a level shifter, and an output buffer. The shift register(210) is used for receiving and outputting the first and the second Vsync signals, a clock signal, and a carry signal. The output controller(220) is used for receiving an odd OE signal and an even OE signal and outputting the carry signal of the shift register. The level shifter(230) is used for converting the carry signal of the output controller to a voltage level according to the clock signal. The output buffer(240) is used for receiving the converted voltage of the level shifter and outputting the converted voltage to an odd and an even gate line according to the odd OE signal and the even OE signal.
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