| 摘要 |
An on-chip differential multi-layer inductor includes a 1<st >partial winding on a 1<st >layer, a 2<nd >partial winding on the 1<st >layer, a 3<rd >partial winding on a 2<nd >layer, a 4<th >partial winding on the 2<nd >layer, and an interconnecting structure. The 1<st >and 2<nd >partial windings on the 1<st >layer are operably coupled to receive a differential input signal. The 3<rd >and 4<th >partial windings on the 2<nd >layer are each operably coupled to a center tap. The interconnecting structure couples the 1<st>, 2<nd>, 3<rd >and 4<th >partial windings such that the 1<st >and 3<rd >partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2<nd >and 4<th >partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.
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