发明名称 MEMORY USING VERTICAL NANO TUBE
摘要 PURPOSE: A memory using a vertical nano-tube is provided to increase a degree of integration and capacity by using a vertical carbon nano-tube. CONSTITUTION: A memory using a vertical nano-tube includes the first electrode array, a dielectric layer, a nano-tube array, the second electrode array, a memory cell, and a gate electrode. The first electrode array is formed with stripe patterns. The dielectric layer(12) is laminated on the first electrode array. A plurality of holes are arranged on the dielectric layer. The nano-tube array is close to the first electrode array in order to emit electrons. The second electrode array is formed on the dielectric layer. The memory cell(15) is installed on the second electrode array in order to capture the electrons from the nano-tube array. The gate electrode(17) is laminated on the memory cell in order to form the electric field around the nano-tube array.
申请公布号 KR20040060370(A) 申请公布日期 2004.07.06
申请号 KR20020087158 申请日期 2002.12.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOI, WON BONG;JUNG, BYEONG HO
分类号 B82B1/00;G11C13/02;H01L27/10;H01L27/115;H01L27/28;H01L29/06;H01L51/00;H01L51/30;(IPC1-7):H01L27/115 主分类号 B82B1/00
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